1. Field of the Invention
The present invention relates to memories and semiconductor devices and, more particularly, to a memory and a semiconductor device, which detect a state of each memory element during a write sequence or an erase sequence to reduce time necessary for writing or erasing.
2. Description of the Related Art
In information equipment, such as computers, high-speed and high-density dynamic random access memories (DRAMs) are widely used as random access memories.
The DRAM is volatile, i.e., it loses information when powered off. Accordingly, a nonvolatile memory which does not lose information when powered off is preferable.
Up-and-coming nonvolatile memories include a ferroelectric memory (FeRAM), a magnetic memory (MRAM), a phase change memory, and a resistance change memory, such as a programmable metallization cell (PMC) or a resistance RAM (RRAM).
Those memories are capable of maintaining written information for a long time even when power is not supplied. Since the above memories are nonvolatile, refresh is unnecessary. Accordingly, power consumption can be reduced by the amount for refresh.
In addition, in the nonvolatile memory, such as a PMC or an RRAM, a memory layer for storing and maintaining information contains a material having such characteristics that the resistance depends on an applied voltage or current. In addition, each memory element has a relatively simple structure in which two electrodes are arranged, with the memory layer therebetween, and a current or a voltage is applied between the two electrodes. Accordingly, each memory element can be easily miniaturized.
The PMC is constructed such that an ionic conductor containing predetermined metal is arranged between two electrodes and any one of the two electrodes also contains the same metal as that in the ionic conductor. The structure has such properties that when a voltage is applied between the two electrodes, the electrical characteristic of the ionic conductor, such as resistance or capacitance, varies. The PMC utilizes the above-mentioned properties.
PCT Japanese Translation Patent Publication No. 2002-536840 (Patent Document 1) discloses an example of the PMC structure. In this example, an ionic conductor includes a solid solution of chalcogenide and metal, e.g., amorphous GeS or amorphous GeSe, and any one of two electrodes contains Ag, Cu, or Zn.
An example of the RRAM structure is disclosed in, e.g., “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, W. W. Zhuan et al., Technical Digest “International Electron Devices Meeting”, 2002, p. 193 (Non-patent Document 1). In this example, a thin film of polycrystalline PrCaMnO3 is arranged between two electrodes and a voltage pulse or a current pulse is applied between the two electrodes, thus significantly changing the resistance of the thin film, serving as a recording layer. The polarity of a voltage pulse applied in recording (writing) information differs from that in erasing information.
An example of another RRAM structure is disclosed in, e.g., “Reproducible Switching Effect in Thin Oxide Films for Memory Applications”, A. Beck et al., Applied Physics Letters, 2000, Vol. 77, pp. 139-141 (Non-patent Document 2). In this example, a thin film of monocrystalline or polycrystalline SrZrO3 doped with a small amount of Cr is arranged between two electrodes and a current is supplied so as to flow between the electrodes, thus changing the resistance of the film, serving as a recording layer.
Non-patent Document 2 shows the I-V characteristic of the recording layer. A threshold voltage upon recording or erasing is ±0.5 V. In this structure, information can be recorded and erased by applying voltage pulses. A necessary pulse voltage is ±1.1 V and a necessary pulse width is 2 ms. In addition, high-speed recording and erasing can be performed. Non-patent Document 2 reports the operation using a voltage pulse width of 100 ns. In this case, a necessary pulse voltage is ±5 V.
In the FeRAM, it is currently difficult to perform nondestructive reading. Unfortunately, since destructive reading is performed, read speed is low. In addition, the FeRAM has a finite number of polarization reversals while reading or writing. This results in a limit in the number of rewritable times.
The MRAM needs a magnetic field in recording. Since the magnetic field is generated by a current supplied to a line, a large amount of current is necessary for recording.
As for the phase change memory, voltage pulses having the same polarity and different levels are applied to record data. In the phase change memory, switching depends on temperature. Disadvantageously, the phase change memory is sensitive to a change in environmental temperature.
In the PMC disclosed in Patent Document 1, the crystallization temperature of amorphous Ges or amorphous GeSe is approximately 200° C. If the ionic conductor is crystallized, the properties are altered. Unfortunately, the material is not capable of resisting high temperatures in a step upon actually manufacturing memory elements, e.g., in a step of forming a CVD insulating film or a protection film.
The memory layers proposed to be used in the PRAMs disclosed in Non-patent documents 1 and 2 are made of crystalline materials, respectively. Accordingly, there are the following problems: Thermal treatment at approximately 600° C. is necessary. It is very difficult to produce a single crystal of each proposed material. In the use of a polycrystal of each material, it is difficult to miniaturize memory elements due to the influence of grain boundary.
To solve the above-mentioned problems, e.g., Japanese Patent Application No. 2004-22121 (Patent Document 2) proposes a memory including memory cells. In this memory, each memory cell includes a memory element and a circuit element, serving as a load, connected in series to the memory element. The memory element has such characteristics that the resistance varies by the application of a voltage of a threshold voltage or higher across the memory element. The resistance of the memory element and that of the circuit element are combined into the combined resistance of the memory cell. The memory has the following characteristics: When a voltage applied between the memory element and the circuit element is equal to or higher than the threshold voltage, the combined resistance, obtained after the resistance of the memory element changes from a high value to a low value, has a substantially constant value independently of the voltage level. According to the proposed memory, stable recording can be realized and time necessary for recording can be reduced.